Payday for MicroUnity

Way back in 1993, when dinosaurs roamed the earth and I was graduating from college, I interviewed with processor designer MicroUnity in Silicon Valley. They had lots of smart people and were doing some amazing things. They had designed a high performance multithreaded processor. They developed highly parallel multimedia applications. They were pushing the bounds of circuit fabrication, with air bridges for interconnects. And they were building their own fab line in Silicon Valley.

“If you want to talk about innovative, they were off the charts. They were looking at making major changes to the microarchitecture and fabrication techniques. They just had too many radical ideas in one package,” [said Lynley Gwennap]. “But from a technology standpoint, they had some really innovative stuff.”

Unfortunately, in the long tradition of ambitious engineering efforts, they went out of business. But this week brought news of some justification for founder John Moussouris and his engineers. Intel agreed to pay $300 million to MicroUnity to settle patent claims related to multithreading. That’s not a huge return over 15 years, considering that MicroUnity raised over $150 million in VC funding in its heyday. But it might lead to other lawsuits and payoffs over MicroUnity’s patents.

The latest from Dan Dobberpuhl

The company started by legendary processor designer Dan Dobberpuhl has finally gone public, announcing a very energy efficient processor based on the PowerPC architecture. They claim their design has five to ten times the performance per watt of mainstream PC processors. (Of course, that’s not setting the bar very high).

The company, P.A. Semi, is pre-announcing their design at this week’s Fall Processor Forum. Working hardware is not expected until the middle of 2006. Their first chip will contain two processor cores and additional support logic. It’s expected to run at 2.5 GHz, and only consume 5 – 13 watts.

Their chip goes to eleven

PCWorld repeats a press release from chip maker Sandbridge. They say that multimode phones could use one Sandbridge chip, instead of separate baseband chips for each network. Fair enough, although established chip makers have a lock on the market.

And they claim a big advantage is that you can use C to program the chip!

Unlike most phone chips, which have to be programmed in assembly language, the SB3000 chips can be programmed in the C language–a significant advantage, according to Strauss.
“People who code in C are a lot cheaper than people who code in assembly language,” Strauss says.

Clone this chip!

Research firm In-Stat claims that new Godson-2 processor being produced in China is a copy of the MIPS architecture. (It also gets my vote for creepiest processor name – it sounds like a bad horror movie.)

China has produced the second version of the first microprocessor produced in the country, according to research firm In-Stat, and it’s largely a copy of the MIPS chip invented by the company of the same name based in the U.S.

Since MIPS hasn’t licensed its technology to the Godson designers, they risk being sued if they sell the chip outside of China. Then again, given how poorly MIPS has been doing lately, maybe it’s not that great a risk. (Pun intended).

IBM licences the Cell chip

IBM has licenced their Cell processor to Mercury Computer Systems for use outside of gaming consoles. IBM Makes Progress On Cell Chip Strategy: “Mercury Computer Systems will use the Cell chips in computers that it makes for the medical imaging, defense, and seismic processing markets.”

A Giant Step for IBM’s New Chip: “Analyst Rick Doherty of tech market researcher Envisioneering Group believes IBM has a chance to address at least one-third of the $3 billion market for embedded chips over time.”

Is day of the architect over? – Is day of the architect over?: “The notion of simply increasing the number of execution pipelines to increase instructions executed per clock cycle has hit the wall, as computer scientists warned it would, somewhere between three and five. Only very unusual hand-optimized loops appear to benefit from more instruction-level parallelism than this. Similarly, the value of supporting multiple threads in hardware appears to roll off after about three to five.”