The Teraflop chip, which consumes just 62 watts at teraflop speeds and which is air-cooled, contains an internal data packet router in each processor tile. It is able to move data among tiles in as little as 1.25 nanoseconds, making it possible to transfer 80 billion bytes a second among the internal cores.
Intel fabricated its 80-core Teraflop Research Chip in its Ireland manufacturing facility, using a state-of-the-art 65-nanometer process. Each core houses two single-cycle floating-point units, which were first described in another ISSCC paper presented two years ago. The 80 cores are arranged in a 10 x 8 two-dimensional mesh network, with each core housing a router with five I/Os–four of its paths going to adjacent processors and one going out vertically to an SRAM chip stacked 3-D style above them.
“Each of our cores measured 3 mm2, including its two independent 32-bit floating-point processors with single-cycle instruction execution,” said Jerry Bautista, director in Intel’s Tera-Scale research program. “A separate 2 Mbytes of SRAM for each core will be mounted on a second chip vertically above the Teraflop Research Chip, with one of the ports in the five-port router communicating with it vertically.”